1. Field of the Invention
The present invention relates to a polishing apparatus, and more particularly to a wafer polishing apparatus for polishing a wafer in the process of fabricating a semiconductor integrated circuit.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows a conventional wafer polishing apparatus.
As shown in FIG. 1, the wafer polishing apparatus primarily includes a wafer chuck 62 for holding a wafer 61 with the surface to be polished being directed downward, the wafer chuck 62 being rotatable in the direction indicated by arrow B by a first drive means (not shown) and reciprocally movable in the directions indicated by arrows C by a reciprocating means (not shown), a surface plate 67 with a polishing cloth pad 64 attached thereto larger in diameter than the wafer 61, the surface plate 67 being rotatable in the direction indicated by arrow A, which is the same direction as direction B, by a second drive means (not shown), a pair of nozzles 65 for supplying a slurry 66 used as a polishing solution to the polishing cloth pad 64, and a pressing means (not shown) for pressing, by way of the wafer chuck 62, the wafer 61 against the polishing cloth pad 64.
The wafer 61 may be held by the wafer chuck 62 by either suction by a vacuum or adherence by wax, a solution, or water. A flange may be used to secure the outer circumferential edge of the wafer 61 in order to prevent displacement of the wafer 61. The polishing cloth pad 64 has a radius which is about twice the diameter of the wafer 61. The size of the surface plate 67 is about five times the size of the wafer 61. The slurry 66 comprises a suspension composed of a mixture of an aqueous solution of KOH and a fine powder of silicon oxide.
To polish the wafer 61, the wafer 61 is fixed to the wafer chuck 62 with the surface to be polished being directed downward, and the wafer 61 is pressed against the surface plate 67 by way of wafer chuck 62. With the slurry 66 supplied from the nozzles 65 to the polishing cloth pad 64, the wafer chuck 62 is rotated in direction B and the surface plate 67 is rotated in directions A, i.e., in the same direction, while at the same time the wafer chuck 62 is reciprocally moved, thereby polishing the wafer 61. At this time, the wafer 61 is pressed against the polishing cloth pad 64 by the pressing means under a pressure of about 500 g/cm.sup.2 through the wafer chuck 62. The slurry 66 is supplied at a rate of about 50 ml/min., the surface plate 67 is rotated at a speed of about 40 rpm, the wafer chuck 62 is rotated at a speed of about 40 rpm, and the wafer chuck 62 makes 10-20 reciprocating movements per minute. In this manner, a plasma CVD silicon oxide film on the surface of the wafer 61 is polished at a rate of about 100 nm/min. The length of the stroke of reciprocal movement of the wafer chuck 62 is about the same as the radius of the wafer 61. Some wafer polishing apparatus have a plurality of wafer chucks to increase the number of wafers that can be polished per unit time.
According to recent processes used in fabricating semiconductor integrated circuits, wafers are polished to a mirror finish, and attempts are also made to flatten surface irregularities of interlayer insulating films and conductive films during the formation of devices on wafer surfaces.
When the conventional wafer polishing apparatus is used to flatten such surface irregularities, the following problems arise: First, it is difficult to optimize the polishing performance. Second, is difficult to provide optimum polishing conditions for different products. Third, the form of the polishing apparatus is not well suited to present semiconductor fabrication environments, and hence there are obstacles to the smooth introduction of the wafer polishing apparatus. These problems will be described in detail below.
Surface irregularities (I) of devices which are produced in the device fabrication process are caused by patterning of interconnections or the like. The surface irregularities have intervals ranging from submicrons to millimeters, and heights of about 1 micron. In addition, surface irregularities (II) may result from ridges in the wafer surface due to irregular wafer film thicknesses before a device is fabricated, or the wafer itself may suffer warpage owing to stresses caused by heating or film growth steps while a device is being fabricated. These surface irregularities (I) and (II) may be simultaneously present at intervals of centimeters and heights of submicrons or more. Polishing must remove the former surface irregularities (I), without removing the latter surface irregularities (II). While the polishing pad has optimized thickness and resilience to flatten the surface irregularities in the conventional polishing apparatus, it is very difficult to make fine adjustment and achieve uniformity of the material of the polishing pad, resulting in a failure to obtain the required polishing performance.
The second problem, i.e., the difficulty of providing optimum polishing conditions for different products, makes it difficult to produce the application-specific integrated circuits (ASICs) that account for a large proportion of presently fabricated types of semiconductor integrated circuits. A high density of surface convexities are polished to a smaller degree than a low density of surface convexities. Different product types have different interconnection patterns, resulting in different densities of wafer surface irregularities. Since different product types therefore have different characteristics when under-going polishing, it is difficult to control the production of ASICs, which are a typical example of an article manufactured in many product types in small quantities.
The third problem, the difficulty of introducing polishing apparatus to present fabrication environments, involves limitations on installation sites for the wafer polishing apparatus. Since the slurry is a mixture of an aqueous solution of KOH and a fine powder of silicon oxide, the polishing apparatus itself is a source of dust particles and alkaline metal. The surface plate and neighboring parts may be enclosed within a sealing structure to prevent contamination of the area, but because the surface plate is large, the sealing structure will also be large in volume and difficult to keep clean. Opening of the sealing structure to service the wafer polishing apparatus results in contamination of the semiconductor fabrication site by dust particles and alkaline metal.